Display Device

ABSTRACT

A display device is disclosed that includes a substrate including a display area and a non-display area that at least partially surrounds the display area. The display device further includes a plurality of pixels in the display area. The display device further includes a data drive unit in the non-display area. The display device further includes a plurality of data lines in the display area. The display device further includes a plurality of data link lines disposed in the non-display area that electrically connect together the data drive unit and the plurality of data lines. The display device further includes high-potential voltage link lines in the non-display area that are configured to supply high-potential voltages to the plurality of pixels. The high-potential voltage link lines include a plurality of holes in regions of the high-potential voltage link lines that overlap the plurality of data link lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority of Republic of Korea PatentApplication No. 10-2021-0184335 filed on Dec. 21, 2021, in the KoreanIntellectual Property Office, which is hereby incorporated by referencein its entirety.

BACKGROUND Field

The present disclosure relates to a display device, and moreparticularly, to a display device capable of suppressing deteriorationin image quality by uniformizing a resistor-capacitor (RC) delay causedby a deviation in length between a plurality of data link lines.

Description of the Related Art

Recently, display devices, which visually display electrical informationsignals, are being rapidly developed in accordance with the full-fledgedentry into the information era. Various studies are being continuouslyconducted to develop a variety of display devices which are thin andlightweight, consume low power, and have improved performance.

As the representative display devices, there may be a liquid crystaldisplay device (LCD), a field emission display device (FED), anelectrowetting display device (EWD), an organic light-emitting displaydevice (OLED), and the like.

Among the display devices, an electroluminescent display device is adisplay device including the organic light-emitting display device andrefers to a display device that autonomously emits light. Unlike aliquid crystal display device, the electroluminescent display devicedoes not require a separate light source and thus may be manufactured asa lightweight, thin display device. In addition, the electroluminescentdisplay device is advantageous in terms of power consumption because theelectroluminescent display device operates at a low voltage. Further,the electroluminescent display device is expected to be adopted invarious fields because the electroluminescent display device is alsoexcellent in implementation of colors, response speeds, viewing angles,and contrast ratios (CRs).

SUMMARY

An object to be achieved by the present disclosure is to provide adisplay device capable of reducing a deviation in RC delay between aplurality of data link lines by adjusting parasitic capacitance betweena high-potential voltage link line and the data link line.

Another object to be achieved by the present disclosure is to provide adisplay device capable of reducing a difference in data load between anouter periphery and a central portion of a substrate.

Objects of the present disclosure are not limited to the above-mentionedobjects, and other objects, which are not mentioned above, can beclearly understood by those skilled in the art from the followingdescriptions.

In one embodiment, a display device comprises: a substrate including adisplay area and a non-display area that at least partially surroundsthe display area; a plurality of pixels in the display area; a datadrive unit in the non-display area; a plurality of data lines in thedisplay area; a plurality of data link lines in the non-display area,the plurality of data link lines electrically connecting together thedata drive unit and the plurality of data lines; and high-potentialvoltage link lines in the non-display, the high-potential voltage linklines configured to supply high-potential voltages to the plurality ofpixels, wherein the high-potential voltage link lines include aplurality of holes in regions of the high-potential voltage link linesthat overlap the plurality of data link lines in the non-display area.

In one embodiment, a display device comprises: a substrate including adisplay area and a non-display area that at least partially surroundsthe display area; a plurality of pixels in the display area; a datadrive unit in the non-display area; a plurality of data lines in thedisplay area; a plurality of data link lines in the non-display area,the plurality of data link lines electrically connecting together thedata drive unit and the plurality of data lines; and high-potentialvoltage link lines in the non-display, the high-potential voltage linklines configured to supply high-potential voltages to the plurality ofpixels, wherein an area of the high-potential voltage link lines thatoverlap the plurality of data link lines in the non-display areadecreases in a direction from a center of the substrate towards an outerperiphery of the substrate as a length of the plurality of data linklines increases from the center of the substrate to the outer peripheryof the substrate.

In one embodiment, a display device comprises: a substrate including adisplay area and a non-display area that at least partially surroundsthe display area; a plurality of pixels in the display area; a datadrive unit in the non-display area; a plurality of data lines in thedisplay area; a plurality of data link lines in the non-display areaincluding a first data link line and a second data link line that islonger than the first link line, the plurality of data link lineselectrically connecting together the data drive unit and the pluralityof data lines; and high-potential voltage link lines in the non-display,the high-potential voltage link lines configured to supplyhigh-potential voltages to the plurality of pixels, wherein a firstportion of the high-potential voltage link lines that overlap the firstlink line has an area that is greater than an area of a second portionof the high-potential voltage link lines that overlap the second linkline that is longer than the first link line.

Other detailed matters of the exemplary embodiments are included in thedetailed description and the drawings.

According to the present disclosure, the proportion of the region inwhich the plurality of holes is disposed varies depending on the area inwhich the high-potential voltage link line overlaps the data link line.Therefore, it is possible to reduce the deviation in RC delay betweenthe outer peripheral region and the central region of the substrate.

According to the present disclosure, it is possible to improve the imagequality of the display device by reducing the deviation in RC delaybetween the plurality of data link lines.

The effects according to the present disclosure are not limited to thecontents exemplified above, and more various effects are included in thepresent specification.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thepresent disclosure will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a schematic top plan view of a display device according to anembodiment of the present disclosure;

FIG. 2 is an enlarged top plan view of area A in FIG. 1 according to anembodiment of the present disclosure;

FIG. 3 is a cross-sectional view of the display device according to theembodiment of the present disclosure;

FIG. 4 is a cross-sectional view taken along line IV-IV′ in FIG. 2according to an embodiment of the present disclosure;

FIG. 5 is a cross-sectional view taken along line V-V′ in FIG. 2according to an embodiment of the present disclosure;

FIG. 6 is an enlarged top plan view of a display device according toanother embodiment of the present disclosure;

FIG. 7 is a cross-sectional view taken along line VII-VII′ in FIG. 6according to the other embodiment of the present disclosure; and

FIG. 8 is a cross-sectional view taken along line VIII-VIII′ in FIG. 6according to the other embodiment of the present disclosure.

DETAILED DESCRIPTION

Advantages and characteristics of the present disclosure and a method ofachieving the advantages and characteristics will be clear by referringto exemplary embodiments described below in detail together with theaccompanying drawings. However, the present disclosure is not limited tothe exemplary embodiments disclosed herein but will be implemented invarious forms. The exemplary embodiments are provided by way of exampleonly so that those skilled in the art can fully understand thedisclosures of the present disclosure and the scope of the presentdisclosure. Therefore, the present disclosure will be defined only bythe scope of the appended claims.

The shapes, sizes, ratios, angles, numbers, and the like illustrated inthe accompanying drawings for describing the exemplary embodiments ofthe present disclosure are merely examples, and the present disclosureis not limited thereto. Like reference numerals generally denote likeelements throughout the specification. Further, in the followingdescription of the present disclosure, a detailed explanation of knownrelated technologies may be omitted to avoid unnecessarily obscuring thesubject matter of the present disclosure. The terms such as “including,”“having,” and “comprising” used herein are generally intended to allowother components to be added unless the terms are used with the term“only”. Any references to singular may include plural unless expresslystated otherwise.

Components are interpreted to include an ordinary error range even ifnot expressly stated.

When the position relation between two parts is described using theterms such as “on”, “above”, “below”, and “next”, one or more parts maybe positioned between the two parts unless the terms are used with theterm “immediately” or “directly”.

When an element or layer is disposed “on” another element or layer, itmay be directly on the other element or layer, or another layer oranother element may be interposed therebetween.

Although the terms “first”, “second”, and the like are used fordescribing various components, these components are not confined bythese terms. These terms are merely used for distinguishing onecomponent from the other components. Therefore, a first component to bementioned below may be a second component in a technical concept of thepresent disclosure.

Same reference numerals generally denote same elements throughout thespecification.

A size and a thickness of each component illustrated in the drawing areillustrated for convenience of description, and the present disclosureis not limited to the size and the thickness of the componentillustrated.

The features of various embodiments of the present disclosure can bepartially or entirely adhered to or combined with each other and can beinterlocked and operated in technically various ways, and theembodiments can be carried out independently of or in association witheach other.

Hereinafter, a display device according to exemplary embodiments of thepresent disclosure will be described in detail with reference toaccompanying drawings.

FIG. 1 is a schematic top plan view of a display device according to anembodiment of the present disclosure. For the convenience ofdescription, FIG. 1 illustrates a substrate 110, a pad part PAD, and adata drive unit DD among various constituent elements of a displaydevice 100. However, the display device may include other elements thanshown in FIG. 1 .

Referring to FIG. 1 , the substrate 110 includes a display area AA and anon-display area NA.

The substrate 110 is a base member for supporting various types ofcomponents of the display device 100 and may be made of an insulatingmaterial. For example, the substrate 110 may be made of a plasticmaterial such as glass or polyimide.

The display area AA is an area in which images are displayed. Aplurality of pixels are disposed in the display area AA. Displayelements for displaying images and drive parts for operating the displayelements may be disposed in the display area AA. For example, in a casein which the display device 100 is an organic light-emitting displaydevice, the display element may be an organic light-emitting elementincluding an anode, an organic layer, and a cathode. The drive part mayinclude various constituent elements such as a power line PL, a gateline, a data line, a thin-film transistor, and a storage capacitor thatserve to operate the organic light-emitting element. Hereinafter, forthe convenience of description, the assumption is made that the displaydevice 100 is the organic light-emitting display device. However, thedisplay device 100 is not limited to the organic light-emitting displaydevice.

Referring to FIG. 1 , the substrate 110 may have variant corner regions.The display area AA may have a shape corresponding to the variant cornerregions of the substrate 110. The corners of the substrate 110 and thecorners of the display area AA may each have a rounded shape. However,the present disclosure is not limited thereto. The substrate 110 and thedisplay area AA may have various shapes suitable for the design of theelectronic apparatus equipped with the display device 100.

The non-display area NA is an area in which no image is displayed.Various lines, various circuits, and the like for operating the displayelements in the display area AA are disposed in the non-display area NA.For example, the data drive unit DD, the link line, the pad part PAD,and the like may be disposed in the non-display area NA.

The non-display area NA may be an area extending from the display areaAA. However, the present disclosure is not limited thereto. Thenon-display area NA may be an area that surrounds the display area AA.

In one embodiment, the non-display area NA includes a first non-displayarea NA1, a bending area BA, and a second non-display area NA2. Thesecond non-display area NA2 is an area extending from the display areaAA. The bending area BA is an area extending from the second non-displayarea NA2. The bending area BA may be bent. The first non-display areaNA1 is an area extending from the bending area BA.

The data drive unit DD, the pad part PAD, and the like may be disposedin the first non-display area NA1. Pads connected to various types ofsignal lines or a PCB are disposed on the pad part PAD. A power supplypad, a data pad, a gate pad, and the like may be disposed on the padpart PAD.

The data drive unit DD may be mounted on or connected to a separate PCBand connected to a display panel through the pad part PAD.Alternatively, the data drive unit DD may be mounted or connected, inthe form of a chip-on-panel (COP) between the pad part PAD and thedisplay area AA. The data drive unit DD includes at least one sourcedrive integrated circuit (IC). The at least one source drive IC issupplied with digital video data and a source timing control signal froma timing controller. The at least one source drive IC generates a datavoltage by converting digital video data into a gamma voltage inresponse to the source timing control signal and supplies the datavoltage through the data line in the display area AA.

A plurality of bending patterns are disposed in the bending area BA. Thebending area BA is an area bent on a final product. Cracks may occurbecause of stress concentrated on the bending patterns disposed in thebending area BA as the bending area BA is bent. Therefore, the bendingpattern may be a pattern having a particular shape in order to reducethe occurrence of cracks. For example, the bending patterns may be madeby repeatedly disposing conductive patterns having at least one of adiamond shape, a rhombic shape, a zigzag shape, and a circular shape.However, the present disclosure is not limited thereto. In addition tothe above-mentioned shapes, the bending pattern may have other shapesfor reducing stress and cracks concentrated on the bending patterns.

The second non-display area NA2 is an area between the bending area BAand the display area AA. The link lines such as the voltage link lineand the data link line may be disposed in the second non-display areaNA2. That is, the second non-display area NA2 serves to transmit asignal, which is outputted from the drive part to the display area AA.In the case in which the substrate 110 includes the variant cornerregions, the second non-display area NA2 may have a shape correspondingto the shape of the substrate 110 and the shape of the display area AA.

FIG. 2 is an enlarged top plan view of area A in FIG. 1 according to oneembodiment. For the convenience of description, FIG. 2 illustrates thesubstrate 110, the pad part PAD, the data drive unit DD, a data line DL,a data link line DLL, and high-potential voltage link lines 160 amongvarious constituent elements of the display device 100. For theconvenience of illustration, FIG. 2 illustrates a dotted line indicatingthe data link line DLL that overlaps the high-potential voltage linkline 160.

Referring to FIG. 2 , the display device 100 may include the displayarea AA and the non-display area NA. The non-display area NA may includethe first non-display area NA1, the second non-display area NA2, and thebending area BA.

In the display area AA, the plurality of data lines DL and a pluralityof gate lines may be disposed to intersect one another. Further, thepixels may be disposed in a matrix shape in each region in which theplurality of data lines DL and the plurality of gate lines intersect oneanother.

The pixels may each include a light-emitting element and a drivethin-film transistor configured to control the amount of current flowingthrough the light-emitting element. The pixel of the display device 100may be supplied with a high-potential voltage through the high-potentialvoltage link line 160 disposed in the non-display area NA. The pixel ofthe display device 100 may be supplied with a low-potential voltagethrough a low-potential voltage link line.

The high-potential voltage link line 160 may be supplied with thehigh-potential voltage from the power supply pad disposed on the padpart PAD and transmit the high-potential voltage to the high-potentialpower line disposed in the display area AA. The high-potential voltagelink lines 160 may include a first high-potential voltage link line 161,a second high-potential voltage link line 162, and a plurality of thirdhigh-potential voltage link lines 163.

The first high-potential voltage link line 161 is disposed in the firstnon-display area NA1. In this case, the first high-potential voltagelink line may be disposed between the bending area BA and the pad partPAD. The first high-potential voltage link line 161 may receive thehigh-potential voltage from the power supply pad of the pad part PAD.

The third high-potential voltage link line 163 is disposed in thebending area BA and connects together the first high-potential voltagelink line 161 and the second high-potential voltage link line 162.Because the third high-potential voltage link line 163 is disposed inthe bending area BA, the third high-potential voltage link line 163 mayhave a pattern having a particular shape for reducing the occurrence ofcracks during a bending process. However, the present disclosure is notlimited thereto. The third high-potential voltage link line 163 mayreceive the high-potential voltage from the first high-potential voltagelink line 161 and transmit the high-potential voltage to the secondhigh-potential voltage link line 162.

The second high-potential voltage link line 162 is disposed in thesecond non-display area NA2. Therefore, the second high-potentialvoltage link line 162 may be disposed between the display area AA andthe bending area BA. Therefore, in the case in which the substrate 110and the display area AA each have the shape corresponding to the variantcorner region, the second high-potential voltage link line 162 may havethe shape corresponding to the shape of the display area AA and theshape of the substrate 110 in the variant corner region. That is, thesecond high-potential voltage link line 162 may have a shape thatmatches a shape of the display area AA and a shape of the substrate 110in the variant corner region. For example, in the case in which thecorner region of the substrate 110 and the corner region of the displayarea AA each have a rounded shape as illustrated in FIG. 2 , a width ofthe second high-potential voltage link line 162 in the variant cornerregion may be less than a width of the second high-potential voltagelink line 162 in the central region. The second high-potential voltagelink line 162 may receive the high-potential voltage from the thirdhigh-potential voltage link line 163 and transmit the high-potentialvoltage to the display area AA.

Next, the pixel of the display device 100 may be supplied with the datavoltage through the data link line DLL disposed in the non-display areaNA and through the data line disposed in the display area. The datavoltage may be supplied to the data drive unit DD through the data padof the pad part PAD. The data drive unit DD is disposed in the firstnon-display area NA1 and provided in the form of an integrated circuit(IC). The data drive unit DD samples and latches the data signalsupplied from the timing controller, converts the data signal into agamma reference voltage, and outputs the gamma reference voltage inresponse to the data timing control signal supplied from the timingcontroller. The data drive unit DD outputs the data signal through theplurality of data link lines DLL.

Because the data drive unit DD and the data pad disposed in the firstnon-display area NA1 are connected to the data line in the display areaAA through the data link line DLL, the data link line DLL is disposedover the first non-display area NA1, the bending area BA, and the secondnon-display area NA2. That is, the data link line DLL may extend fromthe first non-display area NA1 toward the display area AA through thebending area BA. The data link line DLL may be formed as illustrated inFIG. 2 . However, the present disclosure is not limited thereto. Thedata link line DLL formed in the non-display area NA may be connected tothe data line DL formed in the display area AA in various ways.

Because the data link line DLL extends from the data drive unit DDtoward the display area AA through the non-display area NA, there areregions in the first non-display area NA1 and the second non-displayarea NA2 where the data link line DLL overlaps the high-potentialvoltage link line 160. In this case, a plurality of holes H1 may beprovided in the region in which the first and second high-potentialvoltage link lines 161 and 162 overlap the data link line DLL.Therefore, the first and second high-potential voltage link lines 161and 162 may have a mesh pattern in which the plurality of holes H1 arearranged. However, the present disclosure is not limited thereto. Thehigh-potential voltage link line 160 may have various shapes includingthe plurality of holes H1.

A proportion of the region in which the plurality of holes H1 aredisposed may decrease as an area in which the first and secondhigh-potential voltage link lines 161 and 162 overlap the plurality ofdata link lines DLL. That is, a proportion of the region in which theplurality of holes H1 are disposed for each unit area of thehigh-potential voltage link line 160 may increase as the area in whichthe first and second high-potential voltage link lines 161 and 162overlap the plurality of data link lines DLL increases. The plurality ofdata link lines DLL needs to transmit the data signal from the datadrive unit DD to the display area AA of the substrate 110. Therefore,the data link line DLL may have the shortest length at the centralportion of the substrate 110, and the length of the data link line DLLmay increase in a direction toward an outer peripheral region of thesubstrate 110. That is, the data link line DLL disposed at the centralportion of the substrate 110 has a relatively short length and thus haslow resistance. The data link line DLL disposed in the outer peripheralregion of the substrate 110 has a relatively long length and thus hashigh resistance. Therefore, the areas of the first and secondhigh-potential voltage link lines 161 and 162, which overlap the datalink line DLL disposed at the central portion of the substrate 110, needto be larger than the areas of the first and second high-potentialvoltage link lines 161 and 162, which overlap the data link line DLLdisposed in the outer peripheral region of the substrate 110, in orderto reduce a deviation in RC delay between the data link line DLLdisposed at the central portion of the substrate 110 and the data linkline DLL disposed in the outer peripheral region of the substrate 110.Therefore, the proportion of the region in which the plurality of holesH1 are disposed for each unit area of the first and secondhigh-potential voltage link lines 161 and 162 may increase in thedirection from the central portion toward the outer periphery of thesubstrate 110. Thus, as shown in FIG. 2 , a density of holes H1 in thecentral portion of the substrate where the data link line DLL has ashorter width is less than a density of holes H1 in the corners of thesubstrate 110 at the outer periphery of the substrate 110 where the dataline links DLL have longer lengths than the data link lines DLL in thecentral portion of the substrate 110. As a result, a density of theholes H1 increases from the central portion of the substrate 110 towardsthe outer periphery of the substrate 110.

Hereinafter, the constituent elements of the display device 100according to the embodiment of the present disclosure will be describedin more detail with reference to FIGS. 3 to 5 .

FIG. 3 is a cross-sectional view of the display device according to theembodiment of the present disclosure.

Referring to FIG. 3 , the display device 100 according to the embodimentof the present disclosure may include the substrate 110, a buffer layer111, a first thin-film transistor 120, a gate insulating layer 112, afirst interlayer insulating layer 113, a conductive layer 150, a secondinterlayer insulating layer 114, a first planarization layer 115, aconnection electrode 190, a second planarization layer 116, a bank 117,a light-emitting element 130, a sealing part 140, and a conductive layer150.

The substrate 110 may support various constituent elements of thedisplay device 100. The substrate 110 may be made of glass or a plasticmaterial having flexibility. In the case in which the substrate 110 ismade of a plastic material, the substrate 110 may be made of polyimide(PI), for example.

The buffer layer 111 may be disposed on the substrate 110. The bufferlayer 111 may be a single layer made of silicon nitride (SiNx) orsilicon oxide (SiOx) or a multilayer including the above-mentionedlayers. The buffer layer 111 may serve to increase bonding forcesbetween the substrate 110 and layers formed on the buffer layer 111 andblock a leak of an alkaline material from the substrate 110.

The thin-film transistor 120 may be disposed on the buffer layer 111.The thin film transistor 120 may include an active layer 121, a gateelectrode 124, a source electrode 122, and a drain electrode 123. Inthis case, in accordance with design of a pixel circuit, the sourceelectrode 122 may be the drain electrode, and the drain electrode 123may be the source electrode. The active layer 121 of the thin-filmtransistor 120 may be disposed on the buffer layer 111.

The active layer 121 may be made of various materials such aspolysilicon, amorphous silicon, an oxide semiconductor, and the like.The active layer 121 may include a channel region in which a channel isformed when the thin-film transistor 120 operates, and source and drainregions disposed at two opposite sides of the channel region. The sourceregion means a portion of the active layer 121 connected to the sourceelectrode 122. The drain region means a portion of the active layer 121connected to the drain electrode 123.

The gate insulating layer 112 may be disposed on the active layer 121 ofthe thin-film transistor 120. The gate insulating layer 112 may be asingle layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or amultilayer including the above-mentioned layers. The gate insulatinglayer 112 may have a contact hole through which the source electrode 122and the drain electrode 123 of the thin film transistor 120 areconnected to the source and drain regions of the active layer 121 of thethin film transistor 120.

The gate electrode 124 of the thin-film transistor 120 may be disposedon the gate insulating layer 112. The gate electrode 124 may beconfigured as a single layer or multilayer made of any one of molybdenum(Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold(Au), nickel (Ni), neodymium (Nd), and an alloy thereof. The gateelectrode 124 may be formed on the gate insulating layer 112 and overlapthe channel region of the active layer 121 of the thin film transistor120.

The first interlayer insulating layer 113 may be disposed on the gateinsulating layer 112 and the gate electrode 124. The first interlayerinsulating layer 113 may be a single layer made of silicon nitride(SiNx) or silicon oxide (SiOx) or a multilayer including theabove-mentioned layers. The first interlayer insulating layer 113 mayhave a contact hole through which the source and drain regions of theactive layer 121 of the thin film transistor 120 are exposed.

The conductive layer 150 may be disposed on the first interlayerinsulating layer 113. The conductive layer 150 may be a line orelectrode disposed between the gate electrode 124, the source electrode122, and the drain electrode 123.

The second interlayer insulating layer 114 may be disposed on the firstinterlayer insulating layer 113 and the conductive layer 150. The secondinterlayer insulating layer 114 may have the same material as the firstinterlayer insulating layer 113. That is, the second interlayerinsulating layer 114 may be a single layer made of silicon nitride(SiNx) or silicon oxide (SiOx) or a multilayer including theabove-mentioned layers. The second interlayer insulating layer 114 mayhave a contact hole through which the source and drain regions of theactive layer 121 of the thin film transistor 120 are exposed.

The source electrode 122 and the drain electrode 123 of the thin-filmtransistor 120 may be disposed on the second interlayer insulating layer114.

The source electrode 122 and the drain electrode 123 of the thin-filmtransistor 120 may be connected to the active layer 121 of the thin-filmtransistor 120 through the contact holes formed in the gate insulatinglayer 112, the first interlayer insulating layer 113, and the secondinterlayer insulating layer 114. Therefore, the source electrode 122 ofthe thin-film transistor 120 may be connected to the source region ofthe active layer 121 through the contact holes formed in the gateinsulating layer 112, the first interlayer insulating layer 113, and thesecond interlayer insulating layer 114. Further, the drain electrode 123of the thin-film transistor 120 may be connected to the drain region ofthe active layer 121 through the contact holes formed in the gateinsulating layer 112, the first interlayer insulating layer 113, and thesecond interlayer insulating layer 114.

The source electrode 122 and the drain electrode 123 of the thin-filmtransistor 120 may be formed by the same process. Further, the sourceelectrode 122 and the drain electrode 123 of the thin-film transistor120 may be made of the same material. The source electrode 122 and thedrain electrode 123 of the thin-film transistor 120 may each beconfigured as a single layer or multilayer made of any one of molybdenum(Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold(Au), nickel (Ni), and neodymium (Nd) or an alloy thereof.

The first planarization layer 115 may be disposed on the sourceelectrode 122, the drain electrode 123, and the second interlayerinsulating layer 114. As illustrated in FIG. 3 , the first planarizationlayer 115 may have a contact hole through which the drain electrode 123is exposed. The first planarization layer 115 may be an organic materiallayer for flattening an upper portion of the thin-film transistor 120.For example, the first planarization layer 115 may be made of an organicmaterial such as acrylic resin, epoxy resin, phenolic resin, polyamideresin, and polyimide resin. However, the present disclosure is notlimited thereto. The first planarization layer 115 may be an inorganicmaterial layer for protecting the thin-film transistor 120. For example,the first planarization layer 115 may be made of an inorganic materialsuch as silicon nitride (SiNx) or silicon oxide (SiOx). The firstplanarization layer 115 may be a single layer made of silicon nitride(SiNx) or silicon oxide (SiOx) or a multilayer including theabove-mentioned layers.

The connection electrode 190 may be disposed on the first planarizationlayer 115. Further, the connection electrode 190 may be connected to thedrain electrode 123 of the thin-film transistor 120 through the contacthole of the first planarization layer 115. The connection electrode 190may serve to electrically connect the thin-film transistor 120 and thelight-emitting element 130. For example, the connection electrode 190may serve to electrically connect the drain electrode 123 of the thinfilm transistor 120 and a first electrode 131 of the light-emittingelement 130. The connection electrode 190 may be configured as a singlelayer or multilayer made of any one of molybdenum (Mo), copper (Cu),titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni),neodymium (Nd), and an alloy thereof. The connection electrode 190 maybe made of the same material as the source electrode 122 and the drainelectrode 123 of the thin film transistor 120.

The second planarization layer 116 may be disposed on the connectionelectrode 190 and the first planarization layer 115. Further, asillustrated in FIG. 3 , the second planarization layer 116 may have acontact hole through which the connection electrode 190 is exposed. Thesecond planarization layer 116 may be an organic material layer forflattening an upper portion of the thin-film transistor 120. Forexample, the second planarization layer 116 may be made of an organicmaterial such as acrylic resin, epoxy resin, phenolic resin, polyamideresin, and polyimide resin.

The light-emitting element 130 may be disposed on the secondplanarization layer 116. The light-emitting element 130 may include thefirst electrode 131, a light-emitting structure 132, and a secondelectrode 133. The first electrode 131 of the light-emitting element 130may be disposed on the second planarization layer 116. The firstelectrode 131 may be electrically connected to the connection electrode190 through the contact hole formed in the second planarization layer116. Therefore, the first electrode 131 of the light-emitting element130 may be connected to the connection electrode 190 through the contacthole formed in the second planarization layer 116, such that the firstelectrode 131 may be electrically connected to the thin-film transistor120.

The first electrode 131 may have a multilayered structure including atransparent conductive film and an opaque conductive film having highreflection efficiency. The transparent conductive film may be made of amaterial such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO)having a comparatively large work function value. Further, the opaqueconductive film may have a single-layered or multilayered structure madeof Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof. For example, the firstelectrode 131 may have a structure in which the transparent conductivefilm, the opaque conductive film, and the transparent conductive filmare sequentially stacked. However, the present disclosure is not limitedthereto. The first electrode may have a structure in which thetransparent conductive film and the opaque conductive film aresequentially stacked.

Because the display device 100 according to the embodiment of thepresent disclosure is a top emission display device, the first electrode131 may be an anode electrode. When the display device 100 is a bottomemission display device, the first electrode 131 disposed on the secondplanarization layer 116 may be a cathode electrode.

The bank 117 may be disposed on the first electrode 131 and the secondplanarization layer 116. The bank 117 may have an opening portionthrough which the first electrode 131 is exposed. Because the bank 117may define a light-emitting region of the display device 100, the bankmay be referred to as a pixel definition film.

The light-emitting structure 132 including a light-emitting layer may bedisposed on the first electrode 131.

The light-emitting structure 132 of the light-emitting element 130 maybe formed by stacking a positive hole layer, a light-emitting layer, andan electron layer in this order or in the reverse order on the firstelectrode 131. In addition, the light-emitting structure 132 may havefirst and second light-emitting structures facing each other with acharge generation layer interposed therebetween. In this case, thelight-emitting layer of any one of the first and second light-emittingstructures emits blue light, and the light-emitting layer of the otherof the first and second light-emitting structures emits yellow-greenlight. Therefore, white light may be emitted by the first and secondlight-emitting structures. The white light emitted by the light-emittingstructure 132 may enter a color filter positioned on an upper portion ofthe light-emitting structure 132, thereby implementing a color image. Inaddition, the light-emitting structures 132 may each emit color lightcorresponding to each subpixel, thereby implementing a color imagewithout a separate color filter. For example, the light-emittingstructure 132 for a red (R) subpixel may emit red light, thelight-emitting structure 132 for a green (G) subpixel may emit greenlight, and the light-emitting structure 132 for a blue (B) subpixel mayemit blue light.

The second electrode 133 may be further disposed on the light-emittingstructure 132. The second electrode 133 of the light-emitting element130 may be disposed on the light-emitting structure 132 and face thefirst electrode 131 with the light-emitting structure 132 interposedtherebetween. In the display device 100 according to the embodiment ofthe present disclosure, the second electrode 133 may be a cathodeelectrode. The sealing part 140 for suppressing the penetration ofmoisture may be further disposed on the second electrode 133.

The sealing part 140 may include a first inorganic sealing layer 141, anorganic sealing layer 142, and a second inorganic sealing layer 143. Thefirst inorganic sealing layer 141 of the sealing part 140 may bedisposed on the second electrode 133. Further, the organic sealing layer142 may be disposed on the first inorganic sealing layer 141. Inaddition, the second inorganic sealing layer 143 may be disposed on theorganic sealing layer 142. The first inorganic sealing layer 141 and thesecond inorganic sealing layer 143 of the sealing part 140 may each bemade of an inorganic material such as silicon nitride (SiNx) or siliconoxide (SiOx). The organic sealing layer 142 of the sealing part 140 maybe made of an organic material such as acrylic resin, epoxy resin,phenolic resin, polyamide resin, and polyimide resin.

The second inorganic sealing layer 143 may cover top and side surfacesof each of the first inorganic sealing layer 141 and the organic sealinglayer 142. The second inorganic sealing layer 143 may reduce or suppressthe penetration of outside moisture or oxygen into the first inorganicsealing layer 141 and the organic sealing layer 142. In this case, thefirst inorganic sealing layer 141 and the second inorganic sealing layer143 may serve to suppress the penetration of moisture or oxygen. Theorganic sealing layer 142 may serve to flatten an upper portion of thefirst inorganic sealing layer 141. Therefore, the sealing part 140 maycover a gate drive circuit and a dam in the display area AA and thenon-display area NA. However, the configuration of the sealing part 140is not limited thereto.

FIG. 4 is a cross-sectional view taken along line IV-IV′ in FIG. 2according to one embodiment. FIG. 5 is a cross-sectional view takenalong line V-V′ in FIG. 2 according to one embodiment. For theconvenience of description, FIGS. 4 and 5 illustrate only theconstituent elements from the substrate 110 to the second planarizationlayer 116 among various constituent elements of the display device 100.Only the second high-potential voltage link line 162 has been describedwith reference to FIGS. 4 and 5 . The structure of the secondhigh-potential voltage link line 162 may be equally applied to the firsthigh-potential voltage link line 161.

Referring to FIGS. 4 and 5 , the data link line DLL may be disposedbetween the gate insulating layer 112 and the first interlayerinsulating layer 113. That is, the data link line DLL may be formed onthe same layer as the gate electrode 124 of the thin-film transistor 120in the display area AA. However, the present disclosure is not limitedthereto. The data link line DLL may be formed on the same layer as theconductive layer 150 in the display area AA. That is, the data link lineDLL may be disposed between the first interlayer insulating layer 113and the second interlayer insulating layer 114. Specifically, in thefirst non-display area NA1 and the second non-display area NA2, the datalink line DLL may be formed on the same layer as the gate electrode 124or the conductive layer 150. However, the present disclosure is notlimited thereto. The data link line DLL may be made of the same materialand formed on the same layer as various conductive constituent elementson the substrate 110. However, the data link line DLL may be disposed ona layer different from a layer on which the high-potential voltage linkline 160 is disposed.

The high-potential voltage link line 160 may be disposed on the secondinterlayer insulating layer 114. The first planarization layer 115 andthe second planarization layer 116 may be disposed on the secondhigh-potential voltage link line 162. FIGS. 4 and 5 are cross-sectionalviews taken along lines IV-IV′ and V-V′ in FIG. 2 . The secondhigh-potential voltage link line 162 may be disposed on the secondinterlayer insulating layer 114.

As described above, the plurality of holes H1 may be provided in theregion in which the first and second high-potential voltage link lines161 and 162 overlap the data link line DLL. Therefore, the first andsecond high-potential voltage link lines 161 and 162 may have the meshpattern in which the plurality of holes H1 are arranged.

In addition, a proportion of the region occupied by the plurality ofholes H1 for each unit area of the high-potential voltage link line 160may decrease as the area in which the first high-potential voltage linkline 161 and the second high-potential voltage link line 162 overlap theplurality of data link lines DLL decreases. The plurality of data linklines DLL transmit the data signal from the data drive unit DD to thedisplay area AA of the substrate 110. Therefore, the data link line DLLmay have the shortest length at the central portion of the substrate110, and the length of the data link line DLL may increase in thedirection toward the outer peripheral region of the substrate 110. Thatis, the data link line DLL disposed at the central portion of thesubstrate 110 has a relatively short length compared to the data linkline DLL in the outer peripheral region and thus has lower resistancecompared to the resistance of the data link line DLL in the outerperipheral region. The data link line DLL disposed in the outerperipheral region of the substrate 110 has a relatively long lengthcompared to the data link line DLL in the central portion of thesubstrate 110 and thus has higher resistance compared to the resistanceof the data link line DLL in the central portion of the substrate 110.Therefore, the areas of the first and second high-potential voltage linklines 161 and 162, which overlap the data link line DLL disposed at thecentral portion of the substrate 110, need to be larger than the areasof the first and second high-potential voltage link lines 161 and 162,which overlap the data link line DLL disposed in the outer peripheralregion of the substrate 110, in order to reduce a deviation in RC delaybetween the data link line DLL disposed at the central portion of thesubstrate 110 and the data link line DLL disposed in the outerperipheral region of the substrate 110. Therefore, the proportion of theregion in which the plurality of holes H1 are disposed for each unitarea of the first and second high-potential voltage link lines 161 and162 may increase in the direction from the central portion toward theouter periphery of the substrate 110.

Referring to FIGS. 2, 4, and 5 , the proportion of the region in whichthe plurality of holes H1 for each unit area of the first and secondhigh-potential voltage link lines 161 and 162 are disposed may varydepending on the number of holes H1. That is, the sizes of the pluralityof holes H1 are equal to one another in the entire region of thehigh-potential voltage link line 160, but the length of thehigh-potential voltage link line 160 is relatively long. Therefore, thenumber of holes H1 disposed on the high-potential voltage link line 160for each unit area may increase as the region in which thehigh-potential voltage link line overlaps the data link line DLLincreases (or decrease as the region in which the high-potential voltagelink line overlaps the data link line DLL decreases). That is, thelength of the data link line DLL which overlaps the high-potentialvoltage link line 160 at the central portion of the substrate 110 isshort, and the length of the data link line DLL which overlaps thehigh-potential voltage link line 160 at the outer periphery of thesubstrate 110 is long. Therefore, the number of holes H1 on the firstand second high-potential voltage link line 161 and 162 may be greaterat the outer periphery of the substrate 110 than at the central portionof the substrate 110.

In the general display device, the data link line DLL includes a portionextending in an oblique direction instead of a rectilinear direction inorder to reduce the size of the non-display area NA. Therefore, thelength of the data link line may vary depending on the position or thelike of the data link line. For example, among the plurality of datalink lines that receive signals from the same data drive unit, thelength of the data link line disposed at the central portion isrelatively short, whereas the length of the data link line disposed inthe outer peripheral region is relatively long. Therefore, lineresistance of the link line disposed in the outer peripheral region isgreater than line resistance of the link line disposed at the centralportion, which causes a problem in that an RC delay value of the datalink line in the outer peripheral region is larger than an RC delayvalue of the data link line at the central portion.

In addition, a demand for a high-resolution, high-speed operatingproduct increases, and resolution of the display device increases, suchthat a data load of the display panel increases. Therefore, there is aproblem in that the pixel charging time gradually decreases, and theoperating time is insufficient. When the operating time is insufficientas described above, the pixels, which are not yet charged with the datavoltage, are produced because of the RC delay. For this reason, a defectin which colors of the pixels disposed adjacent to each other are mixedmay occur. Therefore, there is a need to reduce the RC delay of the datalink line. Because the RC delay of the data link line is proportional tothe data load of the display panel, the data load needs to be reduced inthe case of a high-resolution, large-area product. In this case, thedata load of the display panel is determined depending on resistance andcapacitance of the data link line, and the resistance and thecapacitance of the data link line increases in proportion to the lengthof the line. Therefore, the data load of the display panel tends tofurther increase in the outer peripheral region in comparison with thecentral portion of the substrate.

Therefore, in the display device 100 according to the embodiment of thepresent disclosure, the plurality of holes H1 are differently disposedfor the respective regions on the first and second high-potentialvoltage link lines 161 and 162 that overlap the data link line DLL.Therefore, the deviation in RC delay between the plurality of data linklines DLL may be reduced. When the plurality of holes H1 are disposed onthe high-potential voltage link line 160, the area in which thehigh-potential voltage link line 160 overlaps the data link line DLLdecreases, such that parasitic capacitance applied to the data link lineDLL may decrease. When the parasitic capacitance applied to the datalink line DLL decreases, the resistance of the data link line DLLremains the same, but the data load decreases. Therefore, the RC delayof the data link line decreases, which may be advantageous in ensuringthe operating time even in the case of the high-resolution, high-speedoperating product.

In addition, in the display device 100 according to the embodiment ofthe present disclosure, a proportion of the region of the plurality ofholes H1 may increase in proportion to the area in which the data linkline DLL overlaps the high-potential voltage link line 160. This is tomaximally decrease the region in which the data link line DLL overlapsthe high-potential voltage link line 160 by disposing a greater numberof holes H1 because the parasitic capacitance increases as the region inwhich the data link line DLL overlaps the high-potential voltage linkline 160 increases. Among the plurality of data link lines DLL, the datalink line DLL disposed at the central portion of the substrate 110 mayhave a relatively short length and thus have low resistance. The regionin which the data link line DLL disposed at the central portion of thesubstrate 110 overlaps the high-potential voltage link line 160 may besmall. On the contrary, among the plurality of data link lines DLL, thedata link line DLL disposed in the outer peripheral region of thesubstrate 110 may have a relatively long length and thus have highresistance. The region in which the data link line DLL disposed in theouter peripheral region of the substrate 110 overlaps the high-potentialvoltage link line 160 may be large. Therefore, the number of holes H1disposed on the first and second high-potential voltage link lines 161and 162 may increase in the direction from the central portion to theouter peripheral region of the substrate 110 so that the parasiticcapacitance applied to the data link line DLL disposed in the outerperipheral region of the substrate 110 is lower than the parasiticcapacitance applied to the data link line disposed at the centralportion of the substrate. Therefore, in the display device 100 accordingto the embodiment of the present disclosure, the number of holes H1varies depending on the area in which the data link line DLL overlapsthe high-potential voltage link line 160. Therefore, it is possible toreduce the deviation in RC delay between the plurality of data linklines and improve the image quality.

FIG. 6 is an enlarged top plan view of a display device according toanother embodiment of the present disclosure. FIG. 7 is across-sectional view taken along line VII-VII′ in FIG. 6 according tothe other embodiment of the present disclosure. FIG. 8 is across-sectional view taken along line VIII-VIII′ in FIG. 6 . For theconvenience of description, FIG. 6 illustrates only the substrate 110,the pad part PAD, the data drive unit DD, the data line DL, the datalink line DLL, and high-potential voltage link lines 260 among variousconstituent elements of a display device 200. For the convenience ofillustration, FIG. 6 illustrates the dotted line indicating the datalink line DLL that overlaps the high-potential voltage link line 260.For the convenience of description, FIGS. 7 and 8 illustrate only theconstituent elements from the substrate 110 to the second planarizationlayer 116 among various constituent elements of the display device 200.Only a second high-potential voltage link line 262 has been describedwith reference to FIGS. 7 and 8 . The structure of the secondhigh-potential voltage link line 262 may be equally applied to a firsthigh-potential voltage link line 261.

Because the data link line DLL extends from the data drive unit DDtoward the display area AA through the non-display area NA, there occursa region in which the data link line DLL overlaps the high-potentialvoltage link line 260. In this case, a plurality of holes H2 may beprovided in the region in which the first and second high-potentialvoltage link lines 261 and 262 overlap the data link line DLL.Therefore, the first and second high-potential voltage link lines 261and 262 may have a mesh pattern in which the plurality of holes H2 arearranged. However, the present disclosure is not limited thereto. Thehigh-potential voltage link line 260 may have various shapes includingthe plurality of holes H2.

The sizes of the plurality of holes H2 of the high-potential voltagelink line 260 may decrease as the area in which the first and secondhigh-potential voltage link lines 261 and 262 overlap the plurality ofdata link lines DLL decreases. That is, a size of holes H2 in thehigh-potential voltage link lines increases from the center of thesubstrate 110 towards the outer periphery of the substrate 110. Theplurality of data link lines DLL needs to transmit the data signal fromthe data drive unit DD to the display area AA of the substrate 110.Therefore, the data link line DLL may have the shortest length at thecentral portion of the substrate 110, and the length of the data linkline DLL may increase in the direction toward the outer peripheralregion of the substrate 110. That is, the data link line DLL disposed atthe central portion of the substrate 110 has a relatively short lengthand thus has low resistance compared to the data link line DLL at theouter periphery of the substrate 110. The data link line DLL disposed inthe outer peripheral region of the substrate 110 has a relatively longlength and thus has high resistance compared to the data link line DLLat the central portion of the substrate 110. Therefore, the areas of thefirst and second high-potential voltage link lines 261 and 262, whichoverlap the data link line DLL disposed at the central portion of thesubstrate 110, need to be larger than the areas of the first and secondhigh-potential voltage link lines 261 and 262, which overlap the datalink line DLL disposed in the outer peripheral region of the substrate110, in order to reduce a deviation in RC delay between the data linkline DLL disposed at the central portion of the substrate 110 and thedata link line DLL disposed in the outer peripheral region of thesubstrate 110. Therefore, the numbers of holes H2 disposed for each unitarea of the first and second high-potential voltage link lines 261 and262 are equal to one another. However, the sizes of the plurality ofholes H2 may increase in the direction from the central portion to theouter periphery of the substrate.

Referring to FIGS. 6 to 8 , the sizes of the plurality of holes H2 mayvary depending on the regions of the first and second high-potentialvoltage link lines 261 and 262. That is, the number of holes H2 for eachunit area (e.g., density) is constant in the entire region, but thelength of the high-potential voltage link line 260 is relatively long.Therefore, the sizes of the plurality of holes H2 disposed on thehigh-potential voltage link line 260 may increase as the region in whichthe high-potential voltage link line 260 overlaps the data link line DLLincreases. That is, the length of the data link line DLL, which overlapsthe high-potential voltage link line 260 at the central portion of thesubstrate 110, is short, and the length of the data link line DLL, whichoverlaps the high-potential voltage link line 260 at the outer peripheryof the substrate 110, is long. Therefore, the sizes of the plurality ofholes H2 on the first and second high-potential voltage link line 261and 262 may be larger at the outer periphery of the substrate 110 thanat the central portion of the substrate 110.

In the display device 200 according to another embodiment of the presentdisclosure, the plurality of holes H2 are differently disposed for therespective regions on the first and second high-potential voltage linklines 261 and 262 that overlap the data link line DLL. Therefore, thedeviation in RC delay between the plurality of data link lines DLL maybe reduced. When the plurality of holes H2 are disposed on thehigh-potential voltage link line 260, the area in which thehigh-potential voltage link line 260 overlaps the data link line DLLdecreases, such that parasitic capacitance applied to the data link lineDLL may decrease. When the parasitic capacitance applied to the datalink line DLL decreases, the resistance of the data link line DLLremains the same, but the data load decreases. Therefore, the RC delayof the data link line decreases, which may be advantageous in ensuringthe operating time even in the case of the high-resolution, high-speedoperating product.

In addition, in the display device 200 according to another embodimentof the present disclosure, the size of the plurality of holes H2 mayincrease in proportion to the area in which the data link line DLLoverlaps the high-potential voltage link line 260. This is to maximallydecrease the region in which the data link line DLL overlaps thehigh-potential voltage link line 260 by increasing the sizes of theplurality of holes H2 because the parasitic capacitance increases as theregion in which the data link line DLL overlaps the high-potentialvoltage link line 260 increases. Among the plurality of data link linesDLL, the data link line DLL disposed at the central portion of thesubstrate 110 may have a relatively short length and thus have lowresistance. The region in which the data link line DLL disposed at thecentral portion of the substrate 110 overlaps the high-potential voltagelink line 260 may be small. On the contrary, among the plurality of datalink lines DLL, the data link line DLL disposed in the outer peripheralregion of the substrate 110 may have a relatively long length and thushave high resistance. The region in which the data link line DLLdisposed in the outer peripheral region of the substrate 110 overlapsthe high-potential voltage link line 260 may be large. Therefore, thesizes of the plurality of holes H2 disposed on the first and secondhigh-potential voltage link lines 261 and 262 may increase in thedirection from the central portion to the outer peripheral region of thesubstrate 110 so that the parasitic capacitance applied to the data linkline DLL disposed in the outer peripheral region of the substrate 110 islower than the parasitic capacitance applied to the data link line DLLdisposed at the central portion of the substrate 110. Therefore, in thedisplay device 200 according to another embodiment of the presentdisclosure, the sizes of the plurality of holes H2 vary depending on thearea in which the data link line DLL overlaps the high-potential voltagelink line 260. Therefore, it is possible to minimize the deviation in RCdelay between the plurality of data link lines DLL and improve the imagequality.

The exemplary embodiments of the present disclosure can also bedescribed as follows:

According to an aspect of the present disclosure, there is provided adisplay device. The display device includes a substrate including adisplay area and a non-display area configured to surround the displayarea. The display device further includes a plurality of pixels disposedin the display area. The display device further includes a data driveunit disposed in the non-display area. The display device furtherincludes a plurality of data lines disposed in the display area. Thedisplay device further includes a plurality of data link lines disposedin the non-display area and configured to connect the data drive unitand the plurality of data lines. The display device further includeshigh-potential voltage link lines disposed in the non-display area andconfigured to supply high-potential voltages to the plurality of pixels.The high-potential voltage link lines include a plurality of holesdisposed in regions in which the high-potential voltage link linesoverlap the plurality of data link lines.

The high-potential voltage link lines may be disposed in a mesh pattern.

The non-display area may include: a first non-display area in which thedata drive unit is disposed; a second non-display area disposed betweenthe first non-display area and the display area; and a bending areadisposed between the first non-display area and the second non-displayarea.

The high-potential voltage link lines may include: a firsthigh-potential voltage link line disposed in the first non-display areaand provided to overlap the plurality of data link lines; a secondhigh-potential voltage link line disposed in the second non-display areaand provided to overlap the plurality of data link lines; and aplurality of third high-potential voltage link lines disposed in thebending area and configured to connect the first and secondhigh-potential voltage link lines.

The plurality of holes may be disposed on the first and secondhigh-potential voltage link lines.

A proportion of a region in which the plurality of holes are disposedmay decrease as an area in which the first and second high-potentialvoltage link lines overlap the plurality of data link lines decreases.

The number of holes for each unit area may decrease as the area in whichthe first and second high-potential voltage link lines overlap theplurality of data link lines decreases.

The sizes of the plurality of holes may decrease as the area in whichthe first and second high-potential voltage link lines overlap theplurality of data link lines decreases.

A proportion of the region in which the plurality of holes are disposedon the first and second high-potential voltage link lines may increasein a direction from a central portion to an outer periphery of thesubstrate.

The substrate may have a variant corner region, the display area mayhave a shape corresponding to the variant corner region, and the secondhigh-potential voltage link line in the variant corner region may have ashape corresponding to the shape of the display area and the shape ofthe substrate.

A corner of the substrate and a corner of the display area may each havea rounded shape.

A width in the variant corner region of the second high-potentialvoltage link line may be smaller than a width in a central region of thesecond high-potential voltage link line.

Although the exemplary embodiments of the present disclosure have beendescribed in detail with reference to the accompanying drawings, thepresent disclosure is not limited thereto and may be embodied in manydifferent forms without departing from the technical concept of thepresent disclosure. Therefore, the exemplary embodiments of the presentdisclosure are provided for illustrative purposes only but not intendedto limit the technical concept of the present disclosure. The scope ofthe technical concept of the present disclosure is not limited thereto.Therefore, it should be understood that the above-described exemplaryembodiments are illustrative in all aspects and do not limit the presentdisclosure. The protective scope of the present disclosure should beconstrued based on the following claims, and all the technical conceptsin the equivalent scope thereof should be construed as falling withinthe scope of the present disclosure.

What is claimed is:
 1. A display device comprising: a substrateincluding a display area and a non-display area that at least partiallysurrounds the display area; a plurality of pixels in the display area; adata drive unit in the non-display area; a plurality of data lines inthe display area; a plurality of data link lines in the non-displayarea, the plurality of data link lines electrically connecting togetherthe data drive unit and the plurality of data lines; and high-potentialvoltage link lines in the non-display, the high-potential voltage linklines configured to supply high-potential voltages to the plurality ofpixels, wherein the high-potential voltage link lines include aplurality of holes in regions of the high-potential voltage link linesthat overlap the plurality of data link lines in the non-display area.2. The display device of claim 1, wherein the high-potential voltagelink lines comprise a mesh pattern.
 3. The display device of claim 1,wherein the non-display area includes: a first non-display area, thedata drive unit in the first non-display area; a second non-display areabetween the first non-display area and the display area; and a bendingarea between the first non-display area and the second non-display area,wherein the high-potential voltage link lines include: a firsthigh-potential voltage link line in the first non-display area, thefirst high-potential voltage link line overlapping a first part of theplurality of data link lines in the first non-display area; a secondhigh-potential voltage link line in the second non-display area, thesecond high-potential voltage link line overlapping a second part of theplurality of data link lines in the second non-display area; and aplurality of third high-potential voltage link lines in the bendingarea, the plurality of third-high potential voltage link lineselectrically connecting the first high-potential voltage link line andthe second high-potential voltage link line, wherein the plurality ofholes are in the first high-potential voltage link line and the secondhigh-potential voltage link line.
 4. The display device of claim 3,wherein a proportion of a region in which the plurality of holes aredisposed decreases as an area in which the first high-potential voltagelink line and the second high-potential voltage link line overlap theplurality of data link lines decreases.
 5. The display device of claim4, wherein a number of holes from the plurality of holes for each unitarea decreases as the area in which the first high-potential voltagelink line and the second high-potential voltage link line overlap theplurality of data link lines decreases.
 6. The display device of claim3, wherein sizes of the plurality of holes decreases as an area in whichthe first high-potential voltage link line and the second high-potentialvoltage link line overlap the plurality of data link lines decreases. 7.The display device of claim 4, wherein a proportion of the region inwhich the plurality of holes are disposed in the first high-potentialvoltage link line and the second high-potential voltage link lineincreases in a direction from a central portion of the substrate to anouter periphery of the substrate.
 8. The display device of claim 3,wherein the substrate has a corner region, the display area has a shapecorresponding to the corner region, and the second high-potentialvoltage link line in the corner region has a shape corresponding to theshape of the display area and the shape of the substrate.
 9. The displaydevice of claim 8, wherein a corner of the substrate has a rounded shapeand a corner of the display area has the rounded shape.
 10. The displaydevice of claim 8, wherein a width in the corner region of the secondhigh-potential voltage link line is less than a width in a centralregion of the second high-potential voltage link line.
 11. The displaydevice of claim 3, wherein the plurality of data link lines extend fromthe first non-display area to the display area.
 12. The display deviceof claim 1, wherein a length of the plurality of data link linesincreases in a direction from a central portion of the substrate towardan outer peripheral region of the substrate.
 13. The display device ofclaim 1, wherein the plurality of data link lines are on a differentlayer than the high-potential voltage link line.
 14. The display deviceof claim 3, wherein first areas of the first high-potential voltage linkline and the second high-potential voltage link line that overlap a datalink line from the plurality of data link lines that is at a centralportion of the substrate are larger than second areas of the firsthigh-potential voltage link line and the second high-potential voltagelink lines that overlap a data link line from the plurality of data linklines that is at an outer peripheral region of the substrate.
 15. Thedisplay device of claim 3, wherein the plurality of holes are arrangeddifferently in different regions on the first high-potential voltagelink line and the second high-potential voltage link lines that overlapthe plurality of data link lines.
 16. The display device of claim 3,wherein a number of holes in the first high-potential voltage link lineand the second high-potential voltage link line increases in a directionfrom a central portion of the substrate to an outer peripheral region ofthe substrate.
 17. The display device of claim 6, wherein a number ofholes for each unit area in the first high-potential voltage link lineand the second high-potential voltage link line is constant.
 18. Thedisplay device of claim 3, wherein sizes of the plurality of holes inthe first high-potential voltage link line and the second high-potentialvoltage link line increase in a direction from a central portion to anouter peripheral region of the substrate.
 19. A display devicecomprising: a substrate including a display area and a non-display areathat at least partially surrounds the display area; a plurality ofpixels in the display area; a data drive unit in the non-display area; aplurality of data lines in the display area; a plurality of data linklines in the non-display area, the plurality of data link lineselectrically connecting together the data drive unit and the pluralityof data lines; and high-potential voltage link lines in the non-display,the high-potential voltage link lines configured to supplyhigh-potential voltages to the plurality of pixels, wherein an area ofthe high-potential voltage link lines that overlap the plurality of datalink lines in the non-display area decreases in a direction from acenter of the substrate towards an outer periphery of the substrate as alength of the plurality of data link lines increases from the center ofthe substrate to the outer periphery of the substrate.
 20. The displaydevice of claim 19, wherein the high-potential voltage link linesincludes a plurality of holes in regions of the high-potential voltagelink lines that overlap the plurality of data link lines.
 21. Thedisplay device of claim 20, wherein a density of the plurality of holesin the high-potential voltage link lines increases from the center ofthe substrate towards the outer periphery of the substrate.
 22. Thedisplay device of claim 21, wherein the plurality of holes have a samesize.
 23. The display device of claim 20, wherein a size of theplurality of holes in the high-potential voltage link lines increasesfrom the center of the substrate towards the outer periphery of thesubstrate.
 24. The display device of claim 23, wherein a density of theplurality of holes in the high-potential voltage link lines is a sameacross the high-potential voltage link lines.
 25. A display devicecomprising: a substrate including a display area and a non-display areathat at least partially surrounds the display area; a plurality ofpixels in the display area; a data drive unit in the non-display area; aplurality of data lines in the display area; a plurality of data linklines in the non-display area including a first data link line and asecond data link line that is longer than the first link line, theplurality of data link lines electrically connecting together the datadrive unit and the plurality of data lines; and high-potential voltagelink lines in the non-display, the high-potential voltage link linesconfigured to supply high-potential voltages to the plurality of pixels,wherein a first portion of the high-potential voltage link lines thatoverlap the first link line has an area that is greater than an area ofa second portion of the high-potential voltage link lines that overlapthe second link line that is longer than the first link line.
 26. Thedisplay device of claim 25, wherein the first portion of thehigh-potential voltage link lines includes a first plurality of holesand the second portion of the high-potential voltage link lines includesa second plurality of holes.
 27. The display device of claim 26, whereina density of the first plurality of holes in the first portion of thehigh-potential voltage link lines is less than a density of the secondplurality of holes in the second portion of the high-potential voltagelink lines.
 28. The display device of claim 26, wherein a size of thefirst plurality of holes in the first portion of the high-potentialvoltage link lines is smaller than a size of the second plurality ofholes in the second portion of the high-potential voltage link lines.